There is a current interest in CMOS active pixel imagers for use as low cost imaging devices. FIG. 1 shows a signal processing system 100 that includes a CMOS active pixel sensor (“APS”) pixel array 230 and a controller 232 that provides timing and control signals to enable the reading out of signals stored in the pixels in a manner commonly known to those skilled in the art. Exemplary arrays have dimensions of M×N pixels, with the size of the array 230 depending on a particular application. The imager pixels are readout a row at a time using a column parallel readout architecture. The controller 232 selects a particular row of pixels in the array 230 by controlling the operation of row addressing circuit 234 and row drivers 240. Charge signals stored in the selected row of pixels are provided on column lines to a readout circuit 242. The pixel signals read from each of the columns, typically a reset signal Vrst and an image signal Vsig for each pixel, are then readout sequentially using a column addressing circuit 244 and supplied to a differential amplifier 212 where the difference signal Vrst−Vsig, representing the light seen by a pixel, is converted to digital information in an analog-to-digital (A/D) converter 214 and provided to an image processor 216.
FIG. 2 shows a portion of the system 100 of FIG. 1 in greater detail. FIG. 2 illustrates a four transistor (4T) CMOS pixel 10 in the pixel array 230. The CMOS pixel 10 generally comprises a photo-conversion device 23 for generating and collecting charge generated by light incident on the pixel 10, and a transfer transistor 17 for transferring photoelectric charges from the photo-conversion device 23 to a sensing node, typically a floating diffusion region 5. The floating diffusion region 5 is electrically connected to the gate of an output source follower transistor 19. The pixel 10 also includes a reset transistor 16 for resetting the floating diffusion region 5 to a predetermined voltage (shown as the array pixel supply voltage Vaa_pix); and a row select transistor 18 for outputting a signal from the source follower transistor 19 to an output line in response to an address signal. In this exemplary pixel 10, a capacitor 20 is also included. One plate of the capacitor 20 is coupled to Vaa_pix cell and the other plate of the capacitor 20 is coupled to the floating diffusion region 5. The capacitor 20 need not be present but does have the benefit, when used, of increasing the charge storing capacity of the floating diffusion node 5.
FIG. 3 is a cross-sectional view of a portion of the pixel 10 of FIG. 2 showing the photo-conversion device 23, transfer transistor 17 and reset transistor 16. The exemplary CMOS pixel 10 photo-conversion device 23 may be formed as a pinned photodiode. The photodiode photo-conversion device 23 has a p-n-p construction comprising a p-type surface layer 22 and an n-type accumulation region 21 within a p-type epitaxial active layer 24 formed on a p-type substrate 11. The photodiode photo-conversion device 23 is adjacent to and partially underneath the transfer transistor 17. The reset transistor 16 is on a side of the transfer transistor 17 opposite the photodiode photo-conversion device 23. As shown in FIG. 3, the reset transistor 16 includes a source/drain region 2. The floating diffusion region 5 is between the transfer and reset transistors 17, 16 and is electrically coupled to the gate of the source follower transistor 19 (shown in FIG. 2) and to one plate of the capacitor 20 (shown in FIG. 2), if the latter is used.
In the CMOS pixel 10 depicted in FIGS. 2-3, electrons are generated by light incident on the photo-conversion device 23 and are stored in the n-type accumulation region 21. These charges are transferred to the floating diffusion region 5 by the transfer transistor 17 when the transfer transistor 17 is activated. The source follower transistor 19 produces an output signal based on the transferred charges. A maximum output signal is proportional to the number of electrons extracted from the n-type accumulation region 21.
Conventionally, a shallow trench isolation (STI) region 3 adjacent the charge accumulation region 21 is used to isolate the pixel 10 from other pixels and devices of the image sensor. The STI region 3 is typically formed using a conventional STI process. The STI region 3 is typically lined with an oxide liner and filled with a dielectric material. Also, the STI region 3 can include a nitride liner which provides several benefits, including improved corner rounding near the STI region 3 corners, reduced stress adjacent the STI region 3, and reduced leakage for the transfer transistor 17.
It is desirable to increase the fill factor and charge storage capacity of an array 230 (FIG. 1). However, the inclusion of a capacitor 20, used to increase charge storage capacity, requires space in the array 230. There is a tradeoff of space: the greater space consumed by capacitors in an array the less available for the photo-conversion devices 23. As such, including capacitors in the array 230 effects the fill factor of the array 230. Therefore, it is desirable to include capacitors to increase charge storage capacity without significantly effecting the fill factor of the array 230.